1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a local silicon oxide nitride oxide silicon (SONOS) cell of a non-volatile memory (NVM) and a method of fabricating the same.
2. Description of the Related Art
Semiconductor memory devices are classified into volatile memories and NVMs according to whether data is lost or maintained, respectively, when power is terminated. Volatile memories, such as DRAMs, lose stored data when power is halted. In contrast, no data is lost in NVMs, such as flash memories, even when power is halted.
Therefore, NVMs have been widely used for devices that are not likely to have a continuous supply of power, such as mobile phone systems and devices that require a memory card for storing music and video data, or for electronic appliances that may abruptly lose power.
Generally, a memory cell of an NVM has a stack type gate structure, and can be a SONOS cell. The SONOS cell is constructed by sequentially stacking, on a first silicon layer, an oxide layer that forms a channel region on a semiconductor device, a nitride layer used as a charge trapping layer, an oxide layer used as a blocking layer, and a second silicon layer used as a control gate electrode.
In a conventional method of fabricating a 1 bit SONOS cell, a charge trapping layer formed by a photolithography process, and more specifically, a length of a nitride layer serving as this charge trapping layer, significantly affects characteristics of a NVM. The nitride layer used as the charge trapping layer is formed by etching that is performed twice. Currently, variation in length of the nitride layer arising from misalignment during etching is one factor that adversely affects uniformity of the local SONOS cell.
FIGS. 1 through 8 illustrate cross-sectional views of stages of a method of fabricating a local SONOS cell of a conventional NVM.
Referring to FIGS. 1 through 4, an ONO layer 101, 102, and 103 is formed by sequentially stacking a first oxide layer 101, a nitride layer 102 and a second oxide layer 103 on a semiconductor substrate 100, as shown in FIG. 1. A first photoresist pattern 104 is formed on the second oxide layer 103, as shown in FIG. 2. The ONO layer 101, 102, and 103 is etched using the first photoresist pattern 104 as an etch mask, with the resultant structure shown in FIG. 3. After removing the first photoresist pattern 104, an upper oxide layer 105 is formed on the resultant structure, as shown in FIG. 4.
Referring to FIGS. 5 through 8, a conductive polysilicon layer 106 is formed on the upper oxide layer 105, as shown in FIG. 5. Then, a second photoresist pattern 111 is formed on the conductive polysilicon layer 106, as shown in FIG. 6. The second photoresist pattern 111 is used as an etch mask during etching of the polysilicon layer 106, the upper oxide layer 105 and the ONO layer 101, 102 and 103, with the resultant structure shown in FIG. 7. Then, the second photoresist pattern 111 is removed, and impurity junction regions 109 and 110 are formed in the substrate 100, as shown in FIG. 8.
However, the conventional method of fabricating the local SONOS cell of the NVM has the following disadvantages.
If misalignment occurs when the first photoresist pattern 104 is formed or used to etch the underlying layers, lengths 107a and 107b of the nitride layer 108 used as the charge trapping layer may be different in adjacent 1 bit SONOS cells.
Also, if misalignment occurs when the second photoresist pattern 111 is formed or used to etch the underlying layers, the lengths 107a and 107b of the nitride layer 108 used as the charge trapping layer may be different in adjacent 1 bit SONOS cells.
The length variation of the nitride layer 108 occurring in adjacent 1 bit SONOS cells arising from the foregoing misalignment degrades uniformity of the 1 bit SONOS cell, which in turn degrades characteristics of the NVM. More specifically, as the length of the nitride layer 108 used as the charge trapping layer increases, data programming characteristics of the 1 bit SONOS cell are improved, but data erasing characteristics of the 1 bit SONOS cell are degraded. On the other hand, as the length of the nitride layer 108 decreases, data erasing characteristics are improved, but data programming characteristics are degraded.